Some conventional lithographic techniques use grating plus trim resolution enhancement techniques such as sidewall image transfer (SIT) techniques to enhance design resolution for the manufacturing of electronic circuits with lithographic processes. These resolution enhancing techniques often result in complex geometries in the trim or block mask designs which in turn give rise to less than desired fidelity or even electrical problems (e.g., short) for certain circuit features. OPC (optical proximity correction) techniques may be used to correct some of these issues but may nevertheless introduce more complex geometries to further exacerbate the root cause of these problems—the complex geometries in the trim or block mask.
Therefore, there exists a need for effective and efficient techniques to enhancing manufacturability in multi-exposure lithography for electronic circuit designs.